Structure for capacitance measurement

ABSTRACT

A structure for being used in measuring a capacitance of a capacitor is provided. The structure includes a plurality of input terminals having an operating voltage and an operating frequency, a first quasi-inverting circuit having a first parasitic capacitor for generating a first current and electrically connected with the input terminals, a second quasi-inverting circuit having a second parasitic capacitor and a first reference capacitor for generating a second current and electrically connected with the first quasi-inverting circuit, and a third quasi-inverting circuit having the capacitor, a third parasitic capacitor and a second reference capacitor for generating a third current and electrically connected with the quasi-inverting circuit.

FIELD OF THE INVENTION

[0001] The present invention relates to a structure, and more particularly to a structure for being used in measuring a capacitance.

BACKGROUND OF THE INVENTION

[0002] In the prior art, the capacitance is obtained by integrating electric charges of a dielectric material. For low leakage current material, eg. silicon dioxide and silicon nitride, the capacitance thereof is not dramatically affected by the lost charges. However, for the material with low dielectric constant, the capacitance value is easily affected by the higher leakage current. Therefore, the influence of the leakage current on measuring the capacitance could not be neglected.

[0003] Because the integrated circuit density is increased, the design of multiple interconnecting lines is needed. However, the circuit characteristics are affected by the parasitic capacitance effect of the multiple interconnecting lines. Generally, the parasitic capacitance of the multiple interconnecting lines is ranged from 10⁻¹⁴ to 10⁻¹² F. In addition, for the material with low dielectric constant, the parasitic capacitance thereof is detected with difficulty by the capacitance measurement devices. In addition, the parasitic capacitance measurement of the multiple interconnecting line is difficult due to the small measurement structure and the leakage current of the insulating materials. Moreover, when the electric charges of the multiple interconnecting lines are changed with time, the parasitic capacitance value measured is not accurate.

[0004] In order to overcome the fore said problems, the present invention provide a structure and a method for measuring the parasitic capacitance of metal interconnecting lines.

SUMMARY OF THE INVENTION

[0005] It is an object of the present invention to provide a structure for being used in measuring capacitance of a capacitor.

[0006] In accordance with the present invention, the structure includes a plurality of terminals, a first quasi-inverting circuit, a second quasi-inverting circuit and a third quasi-inverting circuit.

[0007] The plurality of input terminals have an operating voltage and an operating frequency.

[0008] The first quasi-inverting circuit has a first parasitic capacitor for generating a first current and electrically connected with the input terminals.

[0009] The second quasi-inverting circuit has a second parasitic capacitor and a first reference capacitor for generating a second current and electrically connected with the first quasi-inverting circuit.

[0010] The third quasi-inverting circuit has the capacitor, a third parasitic capacitor and a second reference capacitor for generating a third current and electrically connected with the quasi-inverting circuit.

[0011] In addition, the input terminals are in different phases. The first reference capacitor is connected in parallel to the second parasitic capacitor.

[0012] Preferably, the capacitor is connected with the second reference capacitor in series.

[0013] In accordance with the present invention, the capacitor is a fourth parasitic capacitor needed to be measured.

[0014] Preferably, the first parasitic capacitor, the second parasitic capacitor and the third parasitic capacitor are the same parasitic capacitors.

[0015] Preferably, each parasitic capacitor is made of a first material with low leakage current. The first material is silicon dioxide (SiO₂).

[0016] In addition, the first reference capacitor and the second reference capacitor are the same reference capacitors for reducing leakage current of the capacitor.

[0017] Preferably, each reference capacitance is made of a second material with low leakage current. The second material is silicon dioxide (SiO₂). Furthermore, the operating frequency is ranged from 100 kHz to 10 MHz. The operating voltage is ranged from 1 to 100 V.

[0018] It is another object of the present invention to provide a method for being used in a structure having plural input terminals, a first quasi-inverting circuit, a second quasi-inverting circuit and a third quasi-inverting circuit to measure capacitance of a capacitor.

[0019] In accordance with the present invention, the method includes steps of a) measuring a first current of the first quasi-inverting circuit, b) measuring a second current of the second quasi-inverting circuit, c) measuring a third current of the third quasi-inverting circuit, and d) calculating the capacitance according to the first current, the second current, the third current and a specific formula and reducing leakage current of the capacitance to obtain the capacitance.

[0020] In addition, the first quasi-inverting circuit further includes a first parasitic capacitor.

[0021] The quasi-inverting circuit further includes a second parasitic capacitor and a first reference capacitor.

[0022] The third quasi-inverting circuit further includes the capacitor, a third parasitic capacitor and a second reference capacitor.

[0023] Preferably, the first parasitic capacitor, the second parasitic capacitor and the parasitic capacitor are the same parasitic capacitors.

[0024] Preferably, the first reference capacitor and the second reference capacitor are the same reference capacitors for reducing leakage current of the capacitor.

[0025] In accordance with the present invention, the specific formula is represented by the formula of:

I ₁ =C _(par) f V _(dd)

I ₂=(C _(par) +C _(ref))f V _(dd)

I ₃=(C _(par) +C _(ref) //C _(x))f V _(dd),

[0026] wherein I₁, is the first current, I₂ is the second current, I₃ is the third current, C_(par) is the capacitance of the parasitic capacitor, C_(ref) is the capacitance of the reference capacitor, C_(x) is the capacitance of the capacitor, f is an operating frequency of the input terminals and V_(dd) is an operating voltage of the input terminals.

[0027] The present invention may best be understood through the following descriptions with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a schematic view showing the structure for measuring a capacitance according to the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Please refer to FIG. 1. The structure provided by the present invention includes a first input terminal 101, a second input terminal 102, a first quasi-inverting circuit 11, a second quasi-inverting circuit 12 and a third quasi-inverting circuit 13. The structure is used for reducing the leakage current of a capacitor 131 and a parasitic capacitance of a transistor to accurately measure the capacitance of the capacitor 131.

[0030] The first input terminal 101 and the second input terminal 102 are in different phases and include an operating voltage V_(dd) 15 and an operating frequency f (not shown). The operating frequency f is ranged from 100 kHz to 10 MHz. The operating voltage V_(dd) is ranged from 1 to 100 V.

[0031] The first quasi-inverting circuit 11 is electrically connected with the first input terminal 101 and the second input terminal 102. The first quasi-inverting circuit 11 includes a first parasitic capacitor (not shown) to generate a first current I₁ 16. The second quasi-inverting circuit 12 is electrically connected with the first quasi-inverting circuit 11 and includes a first reference capacitor 14 connected in parallel to a second parasitic capacitor (not shown) to generate a second current I₂ 17.

[0032] The third quasi-inverting circuit 13 is electrically connected with the second quasi-inverting circuit 12 and includes the capacitor 131, a second reference capacitor and a third capacitor (not shown) to generate a third current I₃ 18. The capacitance 131 is connected with the second reference capacitor in series.

[0033] The capacitance C_(x) of the capacitor 131 is accurately measured by calculation according to a specific formula with the first current I₁, the second current I₂ and the third current I₃.

[0034] In addition, the first parasitic capacitor, the second parasitic capacitor and the third parasitic capacitor could be the same parasitic capacitors made of a material with low leakage current. The preferred material with low leakage current is silicon dioxide.

[0035] The first reference capacitor and the second reference capacitor could be the same reference capacitors 14 made of a material with low leakage current for reducing the leakage current of the capacitor 131. The preferred material with low leakage current is silicon dioxide.

[0036] The foresaid specific formula is represented by the formulas as follows.

I ₁ =C _(par) f V _(dd)  (1)

I ₂=(C _(par) +C _(ref))f V _(dd)  (2)

I ₃=(C _(par) +C _(ref) //C _(x))f V _(dd)  (3)

[0037] When the input terminals are activated, the first current I₁ of the first quasi-inverting circuit 11 is measured, and then the second current I₂ of the second quasi-inverting circuit 12 is measured. Subsequently, the third current I₃ of the second quasi-inverting circuit 13 is measured. The C_(par) is the capacitance of the parasitic capacitor, and the Cref is the capacitance of the reference capacitor.

[0038] Then, the equation (4) is derived from (2)-(1) and shown as follows.

C _(ref)=(I ₁ −I ₂)/f V _(dd)  (4)

[0039] The equation (3) is substituted by the equation (1) and shown as follows.

C _(ref) //C _(x)=(I ₃ −I ₁)f V _(dd) =k  (5)

[0040] Then, the capacitance C_(x) of the capacitor 131 is obtained from equations (4) and (5).

C _(x) =k×C _(ref)/(C _(ref) −k),

[0041] wherein k is a constant of (I₃−I₁)f V_(dd).

[0042] While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures. Therefore, the above description and illustration should not be taken as limiting the scope of the present invention which is defined by the appended claims. 

What is claimed is:
 1. A structure for being used in measuring a capacitance of a capacitor, comprising: a plurality of input terminals having an operating voltage and an operating frequency; a first quasi-inverting circuit having a first parasitic capacitor for generating a first current and electrically connected with said input terminals; a second quasi-inverting circuit having a second parasitic capacitor and a first reference capacitor for generating a second current and electrically connected with said first quasi-inverting circuit; and a third quasi-inverting circuit having said capacitor, a third parasitic capacitor and a second reference capacitor for generating a third current and electrically connected with said quasi-inverting circuit.
 2. The structure according to claim 1, wherein said input terminals are in different phases.
 3. The structure according to claim 1, wherein said first reference capacitor is connected in parallel to said second parasitic capacitor.
 4. The structure according to claim 1, wherein said capacitor is connected with said second reference capacitor in series.
 5. The structure according to claim 1, wherein said capacitor is a fourth parasitic capacitor needed to be measured.
 6. The structure according to claim 1, wherein said first parasitic capacitor, said second parasitic capacitor and said third parasitic capacitor are the same parasitic capacitors.
 7. The structure according to claim 6, wherein each said parasitic capacitor is made of a first material with low leakage current.
 8. The structure according to claim 7, wherein said first material is silicon dioxide (SiO₂).
 9. The structure according to claim 1, wherein said first reference capacitor and said second reference capacitor are the same reference capacitors for reducing leakage current of said capacitor.
 10. The structure according to claim 9, wherein each said reference capacitor is made of a second material with low leakage current.
 11. The structure according to claim 10, wherein said second material is silicon dioxide (SiO₂).
 12. The structure according to claim 1, wherein said operating frequency is ranged from 100 kHz to 10 MHz.
 13. The structure according to claim 1, wherein said operating voltage is ranged from 1 to 100 V.
 14. A method for being used in a structure having plural input terminals, a first quasi-inverting circuit, a second quasi-inverting circuit and a third quasi-inverting circuit to measure a capacitance of a capacitor, comprising steps of: a) measuring a first current of said first quasi-inverting circuit; b) measuring a second current of said second quasi-inverting circuit; c) measuring a third current of said third quasi-inverting circuit; and d) calculating said capacitance according to said first current, said second current, said third current and a specific formula and reducing leakage current of said capacitor to obtain said capacitance of said capacitor.
 15. The method according to claim 14, wherein said first quasi-inverting circuit further comprises a first parasitic capacitor.
 16. The method according to claim 15, wherein said quasi-inverting circuit further comprises a second parasitic capacitor and a first reference capacitor.
 17. The method according to claim 16, wherein said third quasi-inverting circuit further comprises said capacitor, a third parasitic capacitor and a second reference capacitor.
 18. The method according to claim 17, wherein said first parasitic capacitor, said second parasitic capacitor and said third parasitic capacitor are the same parasitic capacitors.
 19. The method according to claim 18, wherein said first reference capacitor and said second reference capacitor are the same reference capacitors for reducing leakage current of said capacitor.
 20. The method according to claim 19, wherein said specific formula is represented by the formula of: I ₁ =C _(par) f V _(dd) I ₂=(C _(par) +C _(ref))f V _(dd) I ₃=(C _(par) +C _(ref) //C _(x))f V _(dd), wherein I₁ is said first current, I₂ is said second current, I₃ is said third current, C_(par) is the capacitance of said parasitic capacitor, C_(ref) is the capacitance of said reference capacitor, C_(x) is the capacitance of said capacitor, f is an operating frequency of said input terminals and V_(dd) is an operating voltage of said input terminals. 